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Toshiba Discloses SoCMosaic Custom Chip Hardware/Software Co-Development Strategy and Announces First Two Supported Environments, SwordFish and Seamless
SoCMosaic(TM) Custom Chip Software Design Flow Preserves
Same Programming Environment from Program Start to Silicon,
Can Shave Up to One Year Off Software Development
SAN JOSE, Calif.—(BUSINESS WIRE)—Oct. 9, 2003—
Toshiba America Electronic Components, Inc. (TAEC)* today
announced details of its SoCMosaic(TM) custom chip hardware/software
(HW/SW) co-development strategy designed to help software engineers
developing code for an SoCMosaic custom chip significantly reduce
software development time by as much as one year. The company further
announced that it has selected the WhiteEagle(R) Systems Technology
SwordFish Emulation Platform, an FPGA emulation solution, and the
Mentor Graphics(R) Corporation Seamless(R) Version 5 co-verification
tool as its first two co-development environments.
"Our SoCMosaic custom chip HW/SW co-development strategy builds on
our SoCMosaic custom chip fast, time-to-market approach for IP-rich
custom SoCs. We believe we've come up with a new way of bringing the
time savings and cost efficiencies of HW/SW co-development to our
SoCMosaic custom chip customers," said Richard Tobias, vice president
of the ASIC and Foundry Business Unit at TAEC. "We provide a
development environment that is a front end to a variety of simulation
modes with an application programming interface that further abstracts
the models, making them all look the same to the software. In short,
our SoCMosaic custom chip software design flow ties all the tools
together seamlessly and lets our customers start software development
right away." Mr. Tobias noted that the SwordFish Emulation Platform
from WhiteEagle was designed from the ground up specifically for the
SoCMosaic custom chip program while Seamless from Mentor Graphics
provides a proven, rich co-verification environment.
"As the industry's leading hardware/software co-verification
environment, we value Toshiba's selection of the Mentor Graphics
Seamless technology for its SoCMosaic custom chip strategy," said
Serge Leef, general manager of Mentor Graphics SoC Verification
division. "Collaboration with Toshiba to tailor the Seamless solution
for SoCMosaic custom chip provides a leading-edge co-verification
environment for our mutual customers who are designing the
next-generation communications and digital consumer products."
Compared to conventional approaches, the SoCMosaic custom chip
HW/SW co-development environment allows software development to begin
as much as one year sooner. In addition, this method helps ensure
working first silicon; customers avoid the cost and delay of chip
re-spins due to bugs that could have been found using simulation.
Customers can run their complex software on the SoC while it is in
development, executing their code on a functional model, a mixed
function/register-transfer level (RTL) model and an FPGA emulator that
achieves ten percent of the clock speed of the final SoC. Software
engineers can use the same programming and debugging environment
throughout the entire process, from the C model all the way to the
working end product.
"We are very pleased that Toshiba selected us to provide
technology and services that assist their customers in achieving their
SoCMosaic custom chip design goals," said William Wu, vice president
of Hardware Engineering at WhiteEagle Systems Technology. "Our
approach of extending the SoCMosaic custom chip standardized bus
interface on our system is capable of emulation speeds up to 40MHz and
can model chips as large as 40 million gates. Additionally the
emulation provides a huge benefit to the software development team by
providing a development and verification platform long before the
silicon is ready."
The SoCMosaic custom chip HW/SW co-development environment
provides a front panel that allows software developers to work with
different types of SoC simulation modes. Programmers use the SoCMosaic
custom chip Platform Support Package (PSP) to develop their code which
is independent of the simulation mode. The customer's software can be
migrated seamlessly to any supported run-time environment, including
functional model, mixed functional/gate model, FPGA, the T6TC1XB-0001
development board and the custom SoC. The PSP also provides a
consistent run-time environment for C code. The environment supports a
broad range of programming and debugging tools, including JTAG
in-circuit emulator interfaces.
About the WhiteEagle SwordFish Emulation System
The WhiteEagle SwordFish Emulation System is a hardware box with
an expandable emulation engine and a wide bandwidth host interface.
Customizable I/O interface cards, design automation tools and host
application software round out the product. The bundled EDA and host
application software makes it easy to integrate the SwordFish
Emulation System with existing design flows. This system is targeted
for the customers of the SoCMosaic custom chip platform that want
parallel development of software with hardware, and hardware
verification with real time I/O in the early development phase.
The basic system includes the host interface hardware and the
chassis that houses the backplane with a single blade of the emulation
engine. The customer has the option to upgrade the speed and
capacities of the FPGAs on each emulation blade, upgrade the system to
contain multiple blades and request custom-built I/O cards.
About the Mentor Graphics Seamless HW/SW Co-Verification
Environment
Linking popular software development and debug tools with logic
simulation, the Seamless environment delivers high performance
co-verification months before a hardware prototype can be built. The
Seamless environment enables software and hardware development to be
parallel activities, removing software from the critical path and
reducing the risk of hardware prototype iterations resulting from
integration errors. The Seamless Version 5 tool adds the ability to
analyze code, bus and memory performance. These capabilities allow not
only the validation of hardware/software interactions, but also give
measurement on the quality of the system and guidance on where
improvements can be made. For more information, please go to
www.mentor.com/seamless.
SoCMosaic Custom Chip HW/SW Co-Development Roadmap
TAEC is planning to roll out the following additional tools:
-- System-level architectural simulation.
-- A debug environment.
-- High-level C models for functional execution of the design
before implementation and early software development
before the hardware is ready.
-- New tools for very efficient optimization in area, power
or speed.
Pricing and Availability
The development environment is available now to customers of the
SoCMosaic custom chip program. Pricing consists of tool licensing fees
and engineering costs that depend on project complexity. Specific
tools and models vary according to project and are available from
their respective vendors.
About SoCMosaic Custom Chip
SoCMosaic custom chip is a Soft IP Platform-based design approach
for IP-rich designs that can deliver a custom SoC in as little as six
months. With this approach, customers retain complete control over
their architecture, tapping TAEC's deep IC, system and software
experience to implement the design from RTL integration through
delivery of ICs, including customized on-chip interconnect, power
management and debug/trace support. SoCMosaic custom chip achieves
rapid development of complex SoC designs by using commodity IP blocks,
standardized bus interfaces, a scalable bus system, an RTL test bench
and high-level, cycle-accurate C simulation. Pre-verified, pre-tested
commodity and differentiating IP allows maximum flexibility. System
level support includes hardware and software design (with firmware and
middleware) running on cycle-accurate system-level models for early
development of application software. The T6TC1XB-0001 ARM-based
controller, available now, is aimed at embedded applications that
combine application-specific functions with a single control processor
running Linux or an RTOS, for example, low-end networking and consumer
convergence applications. The SoCMosaic custom chip approach has been
well accepted in the consumer and communications markets and TAEC is
currently working with a number of customers.
*About TAEC
Combining quality and flexibility with design engineering
expertise, TAEC brings a breadth of advanced, next-generation
technologies to its customers. This broad offering includes
semiconductors, flash memory-based storage solutions, optical
communication devices, displays and rechargeable batteries for the
computing, wireless, networking, automotive and digital consumer
markets.
TAEC is an independent operating company owned by Toshiba America,
Inc., a subsidiary of Toshiba, the third largest semiconductor company
worldwide in terms of global sales for the year 2002 according to
Gartner/Dataquest's Worldwide Semiconductor Market Share Ranking.
Toshiba is a world leader in high-technology products with more than
300 major subsidiaries and affiliates worldwide. For additional
company and product information, please visit TAEC's website at
chips.toshiba.com. For technical inquiries, please e-mail
Tech.Questions@taec.toshiba.com.
Editors Note: Reader inquiries please publish:
Tech.Questions@taec.toshiba.com.
All trademarks and registered trademarks are the property of their
respective owners.
Contact:
Toshiba America Electronic Components, Inc.
Deborah Chalmers, 408-526-2454
deborah.chalmers@taec.toshiba.com
or
Agency Contact:
Judy Kahn, 650-948-8881
judith.kahn@comcast.net
or
Reader Inquiries:
Tech.Questions@taec.toshiba.com
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